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DATA SHEET
MOS Integrated Circuit
PD78P322
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The PD78P322 is a version provided by replacing the PD75322's internal mask ROM with one-time PROM or EPROM. Because the one-time PROM version is programmable only once by users, it is ideally suited for small-scale production of many different products, and rapid development and time-to-market of application sets. The EPROM version is reprogrammable, and suited for the evaluation of systems. The PD78P322K, which is the EPROM version, does not maintain planned reliability when used in mass-produced products. Please use only experimentally or for evaluating functions during trial manufacture. Functions are described in detail in the following user's manual. Be sure to read it for designing.
PD78322 User's Manual: IEU-1248
FEATURES
*
PD78322 compatible
* For mass-production, the PD78P322 can be replaced with the PD78322 which incorporates mask ROM
*
Internal PROM: 16,384 x 8 bits * Programmable once only (one-time PROM version without window) * Erasable with ultraviolet rays and electrically programmable (EPROM version with window)
* *
PROM programming characteristics: PD27C256A compatible The PD78P328 is a QTOPTM microcontroller
Remark QTOP microcontroller is a general term for microcontrollers which incorporate one-time PROM, and are totally supported by NEC's programming service (from programming to marking, screening, and verification).
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 20 mm) 74-pin plastic QFP (20 x 20 mm) 68-pin plastic QFJ (950 x 950 mils) 80-pin ceramic WQFN 68-pin ceramic WQFN 74-pin ceramic WQFN Internal ROM One-time PROM One-time PROM One-time PROM EPROM EPROM EPROM Quality Grade Standard Standard Standard Not applicable Standard Standard
PD78P322GF-3B9 PD78P322GJ-5BJ PD78P322L PD78P322K PD78P322KC PD78P322KD
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Functions common to the one-time PROM and EPROM versions are referred to as PROM functions throughout this document. The information in this document is subject to change without notice. Document No. U10435EJ5V0DS00 (5th edition) (Previous No. IC-2485) Date Published December 1995 P Printed in Japan The mark
* shows revised points.
(c)
(c)
1991 1994
PD78P322
PIN CONFIGURATIONS (Top View)
(1) Normal operating mode * 80-pin plastic QFP (14 x 20 mm)
PD78P322GF-3B9
* 80-pin ceramic WQFN
PD78P322K
NC P26/INTP5 P25/INTP4 P24/INTP3 P23/INTP2 P22/INTP1 P21/INTP0 P20/NMI VDD AVDD AVREF P77/AN7 P76/AN6 P75/ANI5 P74/AN4 P73/AN3
P27/INTP6/ TI NC NC P30/TxD P31/RxD P32/SO/SB0 P33/S1/SB1 P34/SCK P80/TO00 P81/TO01 P82/TO02 P83/TO03 P84/TO10 NC P85/TO11 RESET X2 X1 VSS WDTO RTP0/P00 NC TRP1/P01 NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P72/ANI2 NC NC P71/ANI1 P70/ANI0 AVSS VDD P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3 NC NC NC P42/AD2
Caution Connect NC pins to VSS as a measure against noise (can leave open). Remark These pins are compatible with the PD78322GF pins. The PD78P322K does not maintain planned reliability when used in mass-produced products. Please use only experimentally or for evaluating functions during trial manufacture.
2
RTP2/P02 RTP3/P03 RTP4/P04 RTP5/P05 RTP6/P06 RTP7/P07 EA VSS VSS P93/TMD P92/TAS P91/WR P90/RD ASTB P40/AD0 P41/AD1
PD78P322
* 74-pin plastic QFP (20 x 20 mm)
PD78P322GJ-5BJ
* 74-pin ceramic WQFN
PD78P322KD
P42/AD2 P41/AD1 P40/AD0 ASTB P90/RD P91/WR P92/ TAS P93/ TMD VSS EA P07/RTP7 P06/RTP6 P05/RTP5 P04/RTP4 P03/RTP3 P02/RTP2 P01/RTP1 NC 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 1 54 2 3 53 4 52 5 51 6 50 7 49 8 48 9 47 10 46 11 45 12 44 13 43 14 42 15 41 16 40 17 39 18 38 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 NC P56/A14 P57/A15 VDD AVSS P70/AN0 P71/AN1
P00/RTP0 WDTO VSS NC X1 X2 RESET P85/TO11 P84/TO10 P83/TO03 P82/TO02 P81/TO01 P80/TO00 NC P34/SCK P33/SI/SBI P32/SO/SB0 P31/RxD P30/TxD
Caution Connect NC pins to VSS for measures against noise (can leave open). Remark These pins are compatible with the PD78322GJ pins.
NC P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVREF AVDD VDD P20/NMI P21/INTP0 P22/INTP1 P23/INTP2 P24/INTP3 P25/INTP4 P26/INTP5 P27/INTP6 NC
3
PD78P322
* 68-pin plastic QFJ (950 x 950 mils)
PD78P322L
* 68-pin ceramic WQFN
PD78P322KC
P27/INTP6/TI
P26/INTP5
P25/INTP4
P24/INTP3
P23/INTP2
P22/INTP1
P21/INTP0
P77/AN7
P76/AN6
P75/AN5
P74/AN4
P73/AN3
P30/TxD P31/RxD P32/SO/SB0 P33/SI/SB1 P34/SCK P80/TO00 P81/TO01 P82/TO02 P83/TO03 P84/TO10 P85/TO11 RESET X2 X1 VSS WDTO RTP0/P00
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
P72/AN2
P20/NMI
AVREF
AVDD
VDD
P71/AN1 P70/AN0 AVSS VDD P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 P43/AD3
P04/RTP4
P91/WR
P93/TMD
P01/RTP1
P02/RTP2
P03/RTP3
P05/RTP5
P06/RTP6
P07/RTP7
P92/TAS
P90/RD
P40/AD0
P41/AD1
Remark These pins are compatible with the PD78322L pins.
4
P42/AD2
ASTB
VSS
EA
PD78P322
P00-P07 P20-P27 P30-P34 P40-P47 P50-P57 P70-P77 P80-P85 P90-P93 NMI INTP0-INTP6 RTP0-RTP7 TI TxD RxD SB0/SO SB1/SI SCK TO00-TO03 TO10, TO11 : Port 0 : Port 2 : Port 3 : Port 4 : Port 5 : Port 7 : Port 8 : Port 9 : Nonmaskable Interrupt : Interrupt From Peripherals : Real-Time Port : Timer Input : Transmit Data : Receive Data : Serial Bus/Serial Output : Serial Bus/Serial Input : Serial Clock : : RESET X1, X2 WDTO EA TMD TAS WR RD ASTB AD0-AD7 A8-A15 AN0-AN7 AVREF AVSS AVDD VDD VSS NC : Reset : Crystal : Watchdog Timer Output : External Access : Turbo Mode : Turbo Access Strobe : Write Strobe : Read Strobe : Address Strobe : Address/Data Bus : Address Bus : Analog Input : Analog Reference Voltage : Analog VSS : Analog VDD : Power Supply : Ground : No Connection
} Timer Output
5
PD78P322
(2) PROM programming mode (RESET = H, AVDD = L) * 80-pin plastic QFP (14 x 20 mm)
PD78P322GF-3B9
* 80-pin ceramic WQFN
PD78P322K
(G)
(G) NC NC OE CE (L) A8 A10 A11 A12 A13 NC A14 RESET (Open) (G) VSS (Open) A0 NC A1 NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 64 2 63 3 62 4 61 5 60 6 59 7 58 8 57 9 56 10 55 11 54 12 53 13 52 14 51 15 50 16 49 17 48 18 47 19 46 20 45 21 44 22 43 23 42 24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC
A9 VDD AVDD
(G)
(G) NC NC (G) VDD
(Open)
D7 D6 D5 D4 D3 NC NC NC D2
A2 A3 A4 A5 A6 A7 VPP VSS VSS
Cautions 1.
The recommended connection of the unused pins in the PROM programming mode are indicated in parentheses. L G Open : Connect each pin to VSS via a resistor. : Connect the pin to VSS. : Leave the pin unconnected.
2.
Connect NC pins to VSS for measures against noise (can leave open).
The PD78P322K does not maintain planned reliability when used in mass-produced products. Please use only experimentally or for evaluating functions during trial manufacture.
6
(Open)
D0 D1
PD78P322
* 74-pin plastic QFP (20 x 20 mm)
PD78P322GJ-5BJ
* 74-pin ceramic WQFN
PD78P322KD
D2 D1 D0 (Open)
(L)
D3 D4 D5 D6 D7
(L)
NC (L) VDD (G)
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 1 54 2 3 53 4 52 5 51 6 50 7 49 8 48 9 47 10 46 11 45 12 44 13 43 14 42 15 41 16 40 17 39 18 38 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
VSS VPP A7 A6 A5 A4 A3 A2 A1 NC
A0 (Open) VSS NC (G) (Open) RESET A14 A13 A12 A11 A10 A8 NC (L) CE OE
AVDD VDD A9
NC
(G)
Cautions 1.
The recommended connection of the unused pins in the PROM programming mode are indicated in parentheses. L G Open : Connect each pin to VSS via a resistor. : Connect the pin to VSS. : Leave the pin unconnected.
2.
Connect NC pins to VSS as measure against noise.
(G)
NC
7
PD78P322
* 68-pin plastic QFJ (950 x 950 mil)
PD78P322L
* 68-pin ceramic WQFN
PD78P322KC
(G) (G)
OE CE (L) A8 A10 A11 A12 A13 A14 RESET (Open) (G) VSS (Open) A0
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 53 18 52 19 51 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
AVDD
VDD
A9
(G) VDD
(L)
D7 D6 D5 D4 D3
(Open)
VPP
VSS
D0
D1
Caution The recommended connection of the unused pins in the PROM programming mode are indicated in parentheses. L G Open A0-A14 D0-D7 CE OE : Connect each pin to VSS via a resistor. : Connect the pin to VSS. : Leave the pin unconnected. : Address Bus : Data Bus : Chip Enable : Output Enable RESET AVDD VPP NC : :
}
Programming Mode set
: Programming Power Supply : No Connection
8
(L)
D2
A1
A2
A3
A4
A5
A6
A7
BLOCK DIAGRAM
EXU Main RAM (P20) NMI INTP0-INTP5 (P21-P26) PROGRAMMABLE INTERRUPT CONTROLLER
GENERAL REGISTERS 128 bytes & DATA MEMORY 128 bytes
PROM/RAM
BCU X1 X2 RESET ASTB RD WR TAS TMD EA/VPP Note A8-A15 (P50-P57) AD0-AD7 (P40-P47) A0-A14 D0-D7 CE OE
Note
ALU PROM 16 Kbytes / Peripheral RAM 384 bytes
SYSTEM CONTROL & BUS CONTROL & PREFETCH CONTROL
(P80) TO00 (P81) TO01 (P82) TO02 (P83) TO03 (P84) TO10 (P85) TO11 (P27) TI/INTP6
TIMER/COUNTER UNIT (REALTIME PULSE UNIT)
MICRO SEQUENCE CONTROL MICRO ROM
(P34) SCK (P32) SO/SB0 (P33) SI/SB1 (P30) TxD (P31) RxD AVDD AVSS AVREF ANI0-ANI7 (P70-P77) SERIAL INTERFACE (SBI) (UART)
A/D CONVERTER (10 bits)
WDT
PORT
2 WDTO P90-P93 P50-P57 P70-P77 P80-P85 P40-P47 P20-P27 P30-P34 P00-P07 (REALTIME PORT)
2 VSS
VDD
Note
During PROM programming mode
PD78P322
9
PD78P322
CONTENTS
1.
PIN FUNCTIONS ... 11 1.1 Normal Operating Mode ... 11 1.2 PROM Programming Mode (RESET = H, AVDD = L) ... 13 1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ... 14 DIFFERENCES BETWEEN PD78P322 and PD78322 ... 16 PROM PROGRAMMING ... 17 3.1 Operation Mode ... 17 3.2 PROM Write Procedure ... 18 3.3 PROM Read Procedure ... 20 ERASURE CHARACTERISTICS (FOR PD78P322K/KC/KD ONLY) ... 21 OPAQUE FILM ON ERASURE WINDOW (FOR PD78P322K/KC/KD ONLY) ... 21 ONE-TIME PROM VERSION SCREENING ... 21 ELECTRICAL SPECIFICATIONS ... 22 PACKAGE DRAWINGS ... 36 RECOMMENDED SOLDERING CONDITIONS ... 42 DRAWINGS OF CONVERSION SOCKETS AND RECOMMENDED FOOTPRINTS ... 44
2. 3.
4. 5. 6. 7. 8. 9.
APPENDIX A.
*
APPENDIX B. TOOLS ... 48 B.1 Development Tools ... 48 B.2 Evaluation Tools ... 52 B.3 Embedded Software ... 52
10
PD78P322
1. PIN FUNCTIONS
1.1 Normal Operating Mode (1) Port Pins
Pin Name Input/Output Function Alternate Function P00-P07 Input/Output (Output) PORT0 8-bit input/output port Input or output mode can be specified bit-wise. The port can also operate as a real-time output port. P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P40-P47 Input/Output PORT 4 8-bit input/output port Input or output mode can be specified in 8-bit units. P50-P57 Input/Output PORT 5 8-bit input/output port Input or output mode can be specified bit-wise. P70-P77 Input PORT 7 8-bit input-only port P80 P81 P82 P83 P84 P85 P90 P91 P92 P93 Input/Output PORT 9 4-bit input/output port Input or output mode can be specified bit-wise. Input/Output PORT 8 6-bit input/output port Input or output mode can be specified bit-wise. TO00 TO01 TO02 TO03 TO10 TO11 RD WR TAS TMD AN0-AN7 A8-A15 Input/Output PORT 3 5-bit input/output port Input or output mode can be specified bit-wise. Input PORT 2 8-bit input-only port NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6/TI TxD RxD SO/SB0 SI/SB1 SCK AD0-AD7 RTP0-RTP7
11
PD78P322
(2) Non-Port Pins (1/2)
Pin Name Input/Output Function Alternate Function
RTP0-RTP7 Output
Real-time output port which outputs a pulse in synchronization with the trigger signal from P00-P07 the real-time pulse unit (RPU).
INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 NMI
Input
Edge-detected external interrupt request input. The valid edge can be specified in the mode register.
P21 P22 P23 P24 P25 P26 P27/TI
Input
Edge-detected nonmaskable interrupt request input. The rising or falling edge can be selected for the valid edge by setting the mode register.
P20
TI RxD TxD SI SO SB0 SB1 SCK AD0-AD7 A8-A15 RD WR
Input Input Output Input Output Input/Output
External count clock input pin to timer 1 (TM1). Serial data input pin to asynchronous serial interface (UART). Serial data output pin from asynchronous serial interface (UART). Serial data input pin to clocked serial interface in 3-wire mode. Serial data output pin from clocked serial interface in 3-wire mode. Serial data input/output pins to/from clocked serial interface in SBI mode.
P27/INTP6 P31 P30 P33/SB1 P32/SB0 P32/SO P33/SI
Input/Output Input/Output Output Output
Serial clock input/output pin to/from clocked serial interface. Multiplexed address/data bus used when external memory is added. Address bus used when external memory is added. Strobe signal output for external memory read operation. Strobe signal output for external memory write operation.
P34 P40-P47 P50-P57 P90 P91 P92 P93
*
TAS TMD TO00 TO01 TO02 TO03 TO10 TO11 ASTB
Output
Control signal output pins to access turbo access manager (PD71P301). Note
Output
Pulse output from real-time pulse unit.
P80 P81 P82 P83 P84 P85
Output
Timing signal output pin to externally latch low-order address information output from AD0-AD7 for external memory access.
--
WDTO EA
Output Input
Signal output which indicates that watchdog timer generated non-maskable interrupt. For PD78P322, normally connect the EA pin to VDD. When the EA pin is connected to VSS, the PD78P322 enters the ROMless mode and external memory is accessed. The EA pin level cannot be changed during operation.
-- --
Note Turbo access manager (PD71P301) is available for maintenance purposes only.
12
PD78P322
(2) Non-Port Pins (2/2)
Pin Name Input/Output Function Alternate Function AN0-AN7 AVREF AVDD AVSS RESET X1 X2 VDD VSS NC -- -- -- Input Input -- -- Input Input Analog input to A/D converter. A/D converter reference voltage input. A/D converter analog power supply. A/D converter GND. System reset input. Crystal resonator connection pin for system clock generation. To supply external clock, input to the X1 and input inverted signal to the X2 pin (X2 pin can be unconnected.) Positive power supply pin. GND pin. No internal connection. Connect to VSS (can leave open). -- -- -- P70-P77 -- -- -- -- --
1.2 PROM Programming Mode (RESET = H, AVDD = L)
Pin Name Input/Output AVDD RESET A0-A14 D0-D7 CE OE VPP VDD VSS NC Input Input/Output Input Input -- Address bus. Data bus. PROM enable to PROM. Read strobe to PROM. Write power supply. Positive power supply. GND. No internal connection. Connect to VSS (can leave open). Input Function PROM programming mode setting.
13
PD78P322
1.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins Table 1-1 and Figure 1-1 show the pin input/output circuit schematically.
Table 1-1. Pin Input/Output Circuits and Recommended Connection of Unused Pins
Pin Input/Output circuit type P00/RTP0-P07/RTP7 5 Input state: Independently connect to VDD or VSS via a resistor. Output state: Leave Open. P20/NMI P21/INTP0-P26/INTP5 P27/INTP6/TI P30/TxD P31/RxD P32/SO/SB0 P33/SI/SB1 P34/SCK P40/AD0-P47/AD7 P50/A8-P57/A15 P70/AN0-P77/AN7 P80/TO00-P83/TO03 P84/TO10, P85/TO11 P90/RD P91/WR P92/TAS P93/TMD WDTO ASTB EA RESET AVDD AVREF AVSS VPP NC -- -- Connect to VDD. Connect to VSS (can leave open). 3 4 1 2 -- -- -- -- Connect to VDD. Connect to VSS. Leave Open. 5 9 5 Connect to VSS. Input state: Independently connect to VDD or VSS via a resistor. Output state: Leave Open. 5 8 5 Input state: Independently connect to VDD or VSS via a resistor. Output state: Leave Open. 2 Connect to VSS. Recommended connection of unused pins
14
PD78P322
Figure 1-1. Pin Input/Output Circuits
TYPE 1 VDD P-ch TYPE 5 VDD data output disable P-ch N-ch IN/OUT
IN
N-ch input disable
TYPE 2
TYPE 8 VDD IN data output disable P-ch N-ch IN/OUT
Schmitt-triggerred input with hysteresis characteristics
TYPE 3 VDD P-ch
TYPE 9 Comparator + - VREF (Threshold voltage)
IN OUT
P-ch N-ch
N-ch
input enable
TYPE 4 VDD data P-ch
OUT
output disable
N-ch
Push-pull output that can be placed in high impedance (both P-ch and N-ch off).
15
PD78P322
2. DIFFERENCES BETWEEN PD78P322 and PD78322
The PD78P322 is a version provided by replacing the PD78322's on-chip mask ROM with one-time PROM or EPROM. Thus, the PD78P322 and PD78322 are the same in function except for the ROM specifications such as write or verify. Table 2-1 lists the differences between these two products. This Data Sheet describes the PROM specification function. Refer to the PD78322 documents for details of other functions.
Table 2-1. Differences between PD78P322 and PD78322
Item Part Number PD78P322 One-time PROM (programmable only once) Contained * 68-pin plastic QFJ * 74-pin plastic QFP * 80-pin plastic QFP * 68-pin ceramic WQFN * 74-pin ceramic WQFN * 80-pin ceramic WQFN EPROM (reprogrammable)
PD78322
Mask ROM (nonprogrammable) Not contained * 68-pin plastic QFJ * 74-pin plastic QFP * 80-pin plastic QFP
Internal program memory (electrical program) PROM programming pin Package
* * *
Electrical specifications Others
Current dissipations are different. Noise immunity and noise radiation differ because circuit complexity and mask layout are different.
Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To replace the PROM version with the mask ROM version when shifting from experimental production to mass production, evaluate your system by using the CS version (not ES version) of the mask ROM version.
16
PD78P322
3. PROM PROGRAMMING
The PROM incorporated in the PD78P322 is a 16,384 x 8-bit electrically writable PROM. For programming, set the PROM programming mode by using the RESET and AVDD pins. The programming characteristics are compatible with the PD27C256A programming characteristics.
Table 3-1. Pin Function in Programming Mode
Function Address input Data input Chip enable/program pulse Output enable Program voltage Mode control Normal Operating Mode P00-P07, P80, P20, P81-P85 P40-P47 P31 P30 VPP RESET, AVDD Programming Mode A0-A14 D0-D7 CE OE
3.1 Operation Mode To set the program write/verify mode, set RESET = H and AVDD = L. For the mode, the operation mode can be selected by setting the CE and OE pins, as listed in Table 3-2. To read the PROM contents, set the read mode. Connect the unused pins exactly as indicated in Pin Configuration.
Table 3-2. PROM Programming Operation Mode
Mode Program write Program verify Program inhibit Read Output disable Standby RESET H AVDD L CE L H H L L H OE H L H L H L/H +5 V +5 V VPP +12.5 V VDD +6 V D0-D7 Data input Data output High impedance Data output High impedance High impedance
Caution When VPP is set to +12.5 V and VDD is set to +6V, setting both CE and OE to L is prohibited.
17
PD78P322
3.2 PROM Write Procedure The write procedure into PROM is as follows: (1) Fix RESET = H and AVDD = L. Connect other unused pins exactly as indicated in section "Pin Configuration." (2) Supply +6 V to the VDD and +12.5 V to the VPP pin. (3) Supply an initial address. (4) Supply write data. (5) Supply 1 ms program pulse (active low) to the CE pin. (6) Execute the verify mode. Check whether or not the write data is written normally. * When it is written normally: Proceed to step (8). * When it is not written normally: Repeat steps (4) to (6). If the data is not written normally after 25 repetitions of the steps, proceed to step (7). (7) Assume the device to be defective. Stop write operation. (8) Supply write data and X (number of steps (4) to (6) repetitions) x 3 ms program pulses (additional write). (9) Increment the address. (10) Repeat steps (4) to (9) to the last address. Figure 3-1 shows the PROM Write/Verify Timing Steps (2) to (8) above.
Figure 3-1. PROM Write/Verify Timing
X-time repetition Write Verify Additional data write
A0-A14
Address input
Hi-Z D0-D7 Data input
Hi-Z
Data output
Hi-Z Data input
Hi-Z
+12.5 V VPP VDD +6 V VDD VDD 3 X ms
CE (input)
OE (input)
18
PD78P322
Figure 3-2. Write Procedure Flowchart
(1)
WRITE START
(2)
Supply power
(3)
Supply initial address
(4)
Supply write data
(5) Write NG (after 24 repetition or less)
Supply program pulse
(6) Verify mode Write OK
Write NG (at the 25th repetition)
(8)
Make additional write (3X ms pulses)
X: Number of write repetitions
(9)
Increment address
(10) < end address End address (7) Defective device
> end address WRITE END
19
PD78P322
3.3 PROM Read Procedure The read procedure of the PROM contents into the external data bus (D0-D7) is as follows. (1) Fix RESET = H and AVDD = L. Connect other unused pins exactly as indicated in Pin Configuration. (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of the data to be read to the A0-A14 pins. (4) Execute the read mode. (5) The data is output to the D0-D7 pins. Figure 3-3 shows the PROM read timing steps (2) to (5) above.
Figure 3-3. PROM Read Timing
A0-A14
Address input
CE (input)
OE (input)
D0-D7
Hi-Z
Data output
Hi-Z
20
PD78P322
4. ERASURE CHARACTERISTICS (FOR PD78P322K/KC/KD ONLY)
The data written into the PD78P322K/KC/KD program memory can be erased (FFH) and new data can be rewritten into the memory. To erase data, apply light with a wavelength shorter than 400 nm to the window. Normally, apply ultraviolet rays having the 254-nm wavelength. The radiation amount required to completely erase data is as follows: * Ultraviolet strength x erasure time: 15 W*s/cm2 or more * Erasure time: 15 to 20 minutes when a 12,000 W/cm2 ultraviolet lamp is used. However, the time may be prolonged due to ultraviolet lamp performance deterioration, dirty window, etc. For erasure, place an ultraviolet lamp at a position within 2.5 cm from the window. If a filter is attached to the ultraviolet lamp, remove the filter before applying ultraviolet rays.
5.
OPAQUE FILM ON ERASURE WINDOW (FOR PD78P322K/KC/KD ONLY)
If the PD78P322K/KC/KD window is exposed to sunlight or fluorescent lamp light for hours, EPROM data may
be erased and the internal circuit may operate erroneously. To prevent such accidents from occurring, put a protective seal on the window. A protective seal whose quality is guaranteed by NEC is attached to every EPROM version with window at shipment.
6.
ONE-TIME PROM VERSION SCREENING
The one-time PROM versions (PD78P322GF-3B9, 78P322GJ-5BJ, 78P322L) cannot be completely tested by
NEC for shipment because of their structure. For screening, it is recommended to verify PROM after storing the necessary data under the following conditions:
Storage temperature 125C
Storage time 24 hours
NEC provides chargeable services ranging from one-time PROM writing to marking, screening and verification for QTOP microcontroller products. For details, contact an NEC sales representative.
21
PD78P322
7. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C)
Parameter Power supply voltage Symbol VDD AVDD VPP AVSS Input voltage VI1 VI2 Output voltage Output current, low VO IOL All output pins Total for all pins Output current, high IOH All output pins Total for all pins Analog input voltage VIAN Note 2 AVDD > VDD VDD AVDD A/D converter reference input voltage Operating ambient temperature Storage temperature TA Tstg AVREF AVDD > VDD VDD AVDD Note 1 P20/NIM (A9) PIN Test Conditions Ratings -0.5 to +7.0 -0.5 to VDD +0.5 -0.5 to +13.5 -0.5 to +0.5 -0.5 to VDD +0.5 -0.5 to +13.5 -0.5 to VDD +0.5 4.0 90 -1.0 -20 -0.5 to VDD +0.5 -0.5 to AVDD +0.5 -0.5 to VDD +0.3 -0.5 to AVDD +0.3 -10 to +70 -65 to +150 C C V Unit V V V V V V V mA mA mA mA V
Notes 1. Pins except for P20/NMI (A9), P70/AN0-P77/AN7 2. P70/AN0-P77/AN7
*
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, even momentarily. In other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Oscillation frequency 8 MHz fXX 16 MHz TA -10 to +70 C VDD +5.0 V 5%
Capacitance (TA = 25 C, VSS = VDD = 0 V)
Parameter Input capacitance Output capacitance I/O capacitance Symbol CI CO CIO Test Conditions f = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 10 20 20 Unit pF pF pF
22
PD78P322
Oscillator Characteristics (TA = -10 to +70 C, VDD = +5 V5%, VSS = 0 V)
Resonator Ceramic or crystal resonator Recommended Circuit Parameter Oscillation frequency (fXX) MIN. 8 MAX. 16 Unit MHz
X2
X1
VSS
C2
C1
External clock
X1 X2
X1 input frequency (fX)
8
16
MHz
HCMOS Inverter or X1 X2 Open HCMOS Inverter
X1 input rise, fall time (fXR, tXF)
0
20
ns
X1 input high, low level width (tWXH, tWXL)
25
80
ns
Caution When using the system clock oscillator, wire the portion enclosed in broken lines in the figure as follows to avoid adverse influences on the wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines through which a high fluctuating current flows. * Always keep the ground point of the capacitor of the oscillator circuit at the same potential as VSS. Do not connect the power source pattern through which a high current flows. * Do not extract signals from the oscillator.
23
PD78P322
Recommended Oscillator Constants
Ceramic resonator
Manufacturer Name
Part Number
Frequency [MHz]
Recommended Constants C1 [pF] C2 [pF] 30
MURATA
CSA8.00MT CSA12.0MT CSA14.74MXZ040 CSA16.00MX040 CST8.00MTW CST12.0MTW CST14.74MXW0C3 CST16.00MXW0C3
8.0 12.0 14.74 16.0 8.0 12.0 14.74 16.0
30
15
15
Internal
Internal
Crystal resonator
Manufacturer Name
Part Number
Frequency [MHz]
Recommended Constants C1 [pF] C2 [pF] 10
KINSEKI
HC49/U-S HC49/U
8 to 16
10
24
PD78P322
DC Characteristics (TA = -10 to +70 C, VDD = +5 V 5%, VSS = 0 V)
Parameter Input voltage, low Input voltage, high Symbol VIL VIH1 VIH2 Output voltage, low Output voltage, high Input leakage current Output leakage current VDD power supply current VOL VOH ILI ILO IDD1 IDD2 Data retention voltage Data retention current VDDDR IDDDR Note 1 Note 2 IOL = 2.0 mA IOH = -400 A 0 V VI VDD 0 V VO VDD Operation mode HALT mode STOP mode STOP mode VDDDR = 2.5 V VDDDR = 5.0 V 5% 2.5 2 10 10 50 40 20 VDD-1.0 10 10 65 35 Test Conditions MIN. 0 2.2 0.8VDD 0.45 V V TYP. MAX. 0.8 Unit V V
A A
mA mA V
A A
Notes 1. Pins other than mentioned in Note 2. 2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/ INTP6/TI, P32/SO/SB0, P33/SI/SB1, or P34/SCK pins.
25
PD78P322
*
AC Characteristics (TA = -10 to +70 C, VDD = +5 V 5%, VSS = 0 V)
Discontinuous read/write operation (when general-purpose memory is connected)
Parameter System clock cycle time Address setup time (to ASTB ) Address hold time (from ASTB ) Address RD delay time RD address float time Address data input time RD data input time ASTB RD delay time Data hold time (from RD ) RD address active time RD low level width ASTB high level width Address WR delay time ASTB data output time WR data output time ASTB WR delay time Data setup time (to WR ) Data hold time (from WR ) WR ASTB delay time WR low level width Symbol tCYK tSAST tHSTA tDAR tFRA tDAID tDRID tDSTR tHRID tDRA tWRL tWSTH tDAW tDSTOD tDWOD tDSTW tSODW tHWOD tDWST tWWL 42 147 32 42 157 42 0 50 157 37 85 102 40 Test Conditions MIN. 125 32 32 85 0 222 112 MAX. 250 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
26
PD78P322
tCYK-Dependent Bus Timing Definition
Parameter tSAST tHSTA tDAR tDAID tDRID tDSTR tDRA tWRL tWSTH tDAW tDSTOD tDSTW tSODW tHWOD tDWST tWWL Calculation expression 0.5T - 30 0.5T - 30 T - 40 (2.5 + n) T - 90 (1.5 + n) T - 75 0.5T - 20 0.5T - 12 (1.5 + n) T - 30 0.5T - 25 T - 40 0.5T + 40 0.5T - 20 1.5T - 40 0.5T - 30 0.5T - 20 (1.5 + n) T - 30 MIN./MAX. MIN. MIN. MIN. MAX. MAX. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks 1. T = tCYK = 1/fCLK (fCLK is the internal system clock frequency). 2. n is the number of wait cycles defined by user software. 3. Only parameters listed in the table are dependent on tCYK.
27
PD78P322
Serial Operation (TA = -10 to +70 C, VDD = +5 V 5%, VSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK Test Conditions SCK Output SCK Input Serial clock high-level width tWSKL SCK Output SCK Input Serial clock high-level width tWSKH SCK Output SCK Input SI setup time (to SCK ) SI hold time (from SCK ) SCK SO delay time tSRXSK tHSKRX tDSKTX R = 1 k, C = 100 pF Internal divide by 8 External clock Internal divide by 8 External clock Internal divide by 8 External clock MIN. 1 1 420 420 420 420 80 80 210 MAX. Unit
s s
ns ns ns ns ns ns ns
Other operations (TA = -10 to +70C, VDD = +5 V5%, VSS = 0 V)
Parameter NMI high, low-level width Symbol tWNIH, tWNIL INTP0 high, low-level width tWI0H, tWI0L INTP1 high, low-level width tWI1H, tWI1L INTP2 high, low-level width tWI2H, tWI2L INTP3 high, low-level width tWI3H, tWI3L INTP4 high, low-level width tWI4H, tWI4L INTP5 high, low-level width tWI5H, tWI5L INTP6 high, low-level width tWI6H, tWI6L RESET high, low-level width tWRSH, tWRSL TI high, low-level width tWTIH, tWTIL TM1 In the event counter mode 8T tCYK 5 8T tCYK 8T tCYK 8T tCYK 8T tCYK 8T tCYK 8T tCYK 8T tCYK Test Conditions MIN. 5 MAX. Unit
s
s
28
PD78P322
A/D Converter (TA = -10 to +70C, VDD = +5 V5%, VSS = AVSS = 0 V, VDD -0.5 V AVDD VDD)
Parameter Resolution Total error
Note1
Symbol
Test Conditions
MIN. 10
TYP.
MAX.
Unit bit
4.5 V AVREF AVDD 3.4 V AVREF AVDD
0.4 0.7 1/2
%FSR %FSR LSB tCYK tCYK
Quantization error Conversion time Sampling time Zero scale error
Note1
tCONV tSAMP 4.5 V AVREF AVDD 3.4 V AVREF AVDD
144 24 +1.5 +1.5 +1.5 +1.5 +1.5 +1.5 -0.3 3.4 1.0 2.0 STOP mode AVDDDR = 2.5 V AVDDDR = 5 V5% 2.0 10 2.5 4.5 2.5 4.5 2.5 4.5 AVDD AVDD 3.0 6.0 10 50
LSB LSB LSB LSB LSB LSB V V mA mA
Fullscale error
Note1
4.5 V AVREF AVDD 3.4 V AVREF AVDD
Nonlinear error
Note1
4.5 V AVREF AVDD 3.4 V AVREF AVDD
Analog input voltage Basic voltage AVREF current AVDD supply current A/D converter data retention current
Note2
VIAN AVREF AIREF AIDD AIDDDR
*
A A
Notes 1. Quantization error is excluded. 2. When -0.3 V VIAN 0 V, conversion result is 000H. When 0 V < VIAN < AVREF, conversion is executed with 10-bit resolution. When AVREF VIAN AVDD, conversion result is 3FFH.
29
PD78P322
Discontinuous Read Operation
tCYK (CLK)
P50-P57 (output) tSAST P40-P47 (input/output)
Hi-Z
High-order address tDAID
Hi-Z
High-order address
Low-order address (output)
Data (input) tHRID
Hi-Z
Low-order address (output)
Hi-Z
tWSTH ASTB (output) tHSTA tFRA RD (output) tDSTR tDAR tDRID tWRL
tDRA
Discontinuous Write Operation
(CLK)
P50-P57 (output) tSAST P40-P47 (input/output)
Low-order address (output)
High-order address
High-order address
Undefined
Data (output)
Low-order address (output)
tWSTH ASTB (output)
tHWOD
tHSTA tDSTOD
tDWST
WR (output) tDSTW tDWOD tDAW tWWL tSODW
30
PD78P322
Serial Operation
tCYSK tWSKL SCK tDSKTX SO tWSKH
SI tSRXSK tHSKRX
Interrupt Input Timing
tWNIH 0.8VDD 0.8 V
tWNIL
NMI
tWInH
tWInL
INTPn
Remark n = 0-6
31
PD78P322
Reset Input Timing
tWRSH 0.8VDD 0.8 V tWRSL
RESET
TI Pin Input Timing
tWTIH
tWTIL
TI
32
PD78P322
DC Programming Characteristics (TA = 25 5 C, VSS = 0 V)
Parameter Symbol Symbol Test conditions
Note1
MIN.
TYP.
MAX.
Unit
Input voltage, high
VIH
VIH
2.2
VDDP +0.3
V
Input voltage, low Input leakage current Output voltage, high Output voltage, low Input current Output leakage current PROG pin high voltage input current VDDP power supply voltage
VIL ILIP VOH VOL IA9 ILO IIP
VIL ILI VOH VOL -- -- -- 0 VI VDDP IOL = 2.0 mA A9 (P20/NMI) pin 0 VO VDDP, OE = VIN
Note 2
-0.3 IOH = -400 A
0.8 10
V
A
V V
2.4 0.45 10 10 10
A A A
V V V V
VDDP
VDD
Program memory write mode Program memory read mode
5.75 4.5 12.2
6.0 5.0 12.5
6.25 5.5 12.8
VPP power supply voltage
VPP
VPP
Program memory write mode Program memory read mode
VPP = VDDP 10 10 30 30
VDDP power supply current
IDD
IDD
Program memory write mode Program memory read mode CE = VIL, VI = VIH
mA mA
VPP power supply current
IPP
IPP
Program memory write mode CE = VIL, OE = VIH Program memory read mode
10
30
mA
1
100
A
Notes 1. Corresponding PD27C256A symbols. 2. VDDP is VDD pin during the programming mode.
33
PD78P322
AC Programming Characteristics (TA = 25 5 C, VSS = 0 V)
Parameter Address setup time (to CE ) Data OE delay time Input data setup time (to CE ) Address hold time (from CE ) Input data hold time (from CE ) Output data hold time (from OE ) VPP setup time (to CE ) VDDP setup time (to CE ) Initial program pulse width Additional program pulse width Address data output time OE data output time Data hold time (from OE ) Data hold time (from address) Symbol Symbol Test conditions
Note
MIN.
TYP.
MAX.
Unit
tSAC tDDOO tSIDC tHCA tHCID tHOOD tSVPC tSVDC tWL1 tWL2 tDAOD tDOOD tHCOD tHAOD
tAS tOES tDS tAH tDH tDF tVPS tVDS tPW tOPW tACC tOE tDF tOH OE = VIL OE = VIL
2 2 2 2 2 0 2 2 0.95 2.85 1.0 1.05 78.75 2 1 0 0 130 130
s s s s s
ns
s s
ms ms
s s
ns ns
Note
Corresponding PD27C256A symbols.
34
PD78P322
PROM Write Mode Timing
A12-A0 tSAC D7-D0
Hi-Z
Effective address tHOOD
Hi-Z
tHCA Data input tSIDC
Hi-Z
Data input tSIDC
Data output
Hi-Z
tHCID
tHCID
VPP VPP VDDP VDDP +1 VDDP tSVDC VIH CE VIL VIH OE VIL tWL1
tDDOO
tSVPC
VDDP
tDOOD
tWL2
Cautions 1. Apply VDDP before VPP and remove it after VPP. 2. VPP must not exceed +13 V, including the overshoot.
PROM Read Mode Timing
A12-A0
Effective address
OE tDAOD D7-D0 Hi-Z tDOOD
tHCOD
tHAOD Data output Hi-Z
35
PD78P322
8. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x20)
A B
64 65
41 40 detail of lead end
D
C
S
80 1
25 24
F
G
H
IM
J K
P
N NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
L P80GF-80-3B9-2 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 0.8 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.15 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795 +0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 -0.009
+0.008
M
0.031+0.009 -0.008 0.006+0.004 -0.003 0.006 0.106 0.004 0.004 0.119 MAX.
36
55
Q
PD78P322
74 PIN PLASTIC QFP ( 20)
A B
F2
56 57
38 37
detail of lead end
C
D
S
F1
74 1
19 18
G1
G2 H I
M
J K
P
N
NOTE
L
ITEM A B C D F1 F2 G1 G2 H I J K L M N P Q R S MILLIMETERS 23.20.4 20.00.2 20.00.2 23.20.4 2.0 1.0 2.0 1.0 0.400.10 0.20 1.0 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.10 3.7 0.10.1 55 4.0 MAX. INCHES 0.913 +0.017 -0.016 0.787 +0.009 -0.008 0.787 +0.009 -0.008 0.913 +0.017 -0.016 0.079 0.039 0.079 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.146 0.0040.004 55 0.158 MAX. S74GJ-100-5BJ-3
Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition.
M
Q
R
37
PD78P322
68 PIN PLASTIC QFJ (
950 mil)
A B
F
E
J
G
H
T K M N
M
Q
I
P
U
C D
68 1
P68L-50A1-2 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K M N P Q T U MILLIMETERS 25.2 0.2 24.20 24.20 25.2 0.2 1.94 0.15 0.6 4.4 0.2 2.8 0.2 0.9 MIN. 3.4 1.27 (T.P.) 0.40 1.0 0.12 23.12 0.20 0.15 R 0.8 0.20 +0.10 -0.05 INCHES 0.992 0.008 0.953 0.953 0.992 0.008 0.076+0.007 -0.006 0.024 0.173+0.009 -0.008 0.110+0.009 -0.008 0.035 MIN. 0.134 0.050 (T.P.) 0.016+0.004 -0.005 0.005 0.910+0.009 -0.008 0.006 R 0.031 0.008+0.004 -0.002
38
PD78P322
80 PIN CERAMIC WQFN
A B K Q
T 80
W S
D
C
U
H
I
M
1 J R
E
F
G
X80KW-80A-1 NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K Q R S T U W MILLIMETERS 20.0 0.4 19.0 13.2 14.2 0.4 1.64 2.14 4.064 MAX. 0.51 0.10 0.08 0.8 (T.P.) 1.0 0.2 C 0.5 0.8 1.1 R 3.0 12.0 0.75 0.2 INCHES 0.787+0.017 -0.016 0.748 0.520 0.559 0.016 0.065 0.084 0.160 MAX. 0.020 0.004 0.003 0.031 (T.P.) 0.039 -0.008 C 0.020 0.031 0.043 R 0.118 0.472 0.030 -0.009
+0.008 +0.009
39
PD78P322
74 PIN CERAMIC WQFN
A B
K
Q
T
D C
74
W
Y
U
H
I
M
1 J R
E
F
G
X74KW-100A-1 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K Q R S T U W Y MILLIMETERS 20.0 0.4 18.0 18.0 20.0 0.4 1.94 2.14 4.0 MAX. 0.51 0.10 0.10 1.0 (T.P.) 1.0 0.2 C 0.3 2.0 2.0 R 2.0 10.0 0.7 0.2 C 1.5 INCHES 0.787+0.017 -0.016 0.709 0.709 0.787+0.017 -0.016 0.076 0.084 0.158 MAX. 0.020 0.004 0.004 0.039 (T.P.) 0.039 -0.008 C 0.012 0.079 0.079 R 0.079 0.394 0.028 -0.009 C 0.059
+0.008 +0.009
40
S
PD78P322
68 PIN CERAMIC WQFN
A B K
L
Q P
T
68 1
U
D
C
Y H
G E F
IM J R
X68KW-50A-1 NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D E F G H I J K L P Q R S T U Y MILLIMETERS 24.13 0.4 21.5 21.5 24.13 0.4 1.65 2.03 3.50 MAX. 0.64 0.10 0.12 1.27 (T.P.) 1.27 0.2 2.16 0.2 R 0.2 C 1.02 1.905 1.905 R 3.0 12.0 C 0.5 INCHES 0.950 0.016 0.846 0.846 0.950 0.016 0.065 0.080 0.138 MAX. 0.025+0.005 -0.004 0.005 0.05 (T.P.) 0.05 0.008 0.085 0.008 R 0.008 C 0.04 0.075 0.075 R 0.118 0.472 C 0.020
S
41
PD78P322
9. RECOMMENDED SOLDERING CONDITIONS
It is recommended that this device be soldered under the following conditions. For details on the recommended soldering conditions, refer to information document "Semiconductor Devices Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended, please contact your NEC sales representative.
Table 9-1. Soldering Conditions for Surface Mount Devices (1/2)
*
PD78P322GF-3B9: 80-pin plastic QFP (14 x 20 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (210C min.), Number of times: 2 max., Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. VPS Package peak temperature: 215C, Time: 40 seconds max. (200C min.), Number of times: 2 max., Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. Soldering bath temperature: 260C max., Time: 10 seconds max., Number of times: 1, Preheating temperature: 120C max. (package surface temperature), Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125C). Pin temperature: 300C max., Time: 3 seconds max. (per pin) VP15-207-2 Recommended Soldering Code IR35-207-2
Wave soldering
WS60-207-1
Partial heating
--
PD78P322GJ-5BJ: 74-pin plastic QFP (20 x 20 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 230C, Time: 30 seconds max. (210C min.), Number of times: 1, Maximum number of days: 7 daysNote (thereafter, 10 hours of prebaking is required at 125C) Package peak temperature: 215C, Time: 40 seconds max. (200C min.), Number of times: 1, Maximum number of days: 7 daysNote (thereafter, 20 hours of prebaking is required at 125C) Pin temperature: 300C max., Time: 3 seconds max. (per pin) Recommended Soldering Code IR30-107-1
VPS
VP15-107-1
Partial heating
--
Note Number of days after unpacking the dry pack. Storage conditions are 25C and 65% RH max. Caution Do not use different soldering methods together (except for partial heating method).
42
PD78P322
Table 9-1. Soldering Conditions for Surface Mount Devices (2/2)
*
PD78P322L: 68-pin plastic QFJ (950 x 950 mils)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (210C min.), Number of times: 2 max., Maximum number of days: 7 daysNote (thereafter, 36 hours of prebaking is required at 125C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. Package peak temperature: 215C, Time: 40 seconds max. (200C min.), Number of times: 2 max., Maximum number of days: 7 daysNote (thereafter, 36 hours of prebaking is required at 125C) < Cautions > (1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow. (2) Do not perform flux cleaning with water after the first reflow. Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin) -- Recommended Soldering Code IR35-367-2
VPS
VP15-367-2
Note Number of days after unpacking the dry pack. Storage conditions are 25C and 65% RH max. Caution Do not use different soldering methods together (except for partial heating method).
43
PD78P322
APPENDIX A. DRAWINGS OF CONVERSION SOCKETS AND RECOMMENDED FOOTPRINTS
(1) EV-9200G-74
Figure A-1. Drawing of Conversion Socket (EV-9200G-74) (For reference only)
A E B F M N O
R
S D C T
INCHES 0.984 0.801 0.801 0.984 4-C 0.11 0.039 0.433 0.866 0.972 0.197 0.866 0.972 0.315 0.307 0.098 0.079 0.053 0.014+0.004 -0.005
K
Q L
EV-9200G-74
C 1.5 1 No.1 pin index P
G H I EV-9200G-74-G0 ITEM A B C D E F G H I J K L M N O P Q R S T MILLIMETERS 25.0 20.35 20.35 25.0 4-C 2.8 1.0 11.0 22.0 24.7 5.0 22.0 24.7 8.0 7.8 2.5 2.0 1.35 0.35 0.1
J
2.3 1.5
0.091 0.059
44
PD78P322
Figure A-2. Recommended Footprint of Conversion Socket (EV-9200G-74) (For reference only)
G
J
D
E
F
K
C B A
EV-9200G-74-P0 ITEM A B C D E F G H I J K Caution MILLIMETERS 25.7 21.0 1.00.02 x 18=18.00.05 INCHES 1.012 0.827 0.039+0.002 x -0.001 0.709=0.709 +0.002 -0.003
1.00.02 x 18=18.00.05 0.039+0.002 x 0.709=0.709 +0.002 -0.001 -0.003 21.0 25.7 11.00 0.08 5.00 0.08 0.6 0.02 0.827 1.012 0.433+0.004 -0.003 0.197+0.003 -0.004 0.024+0.001 -0.002
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.062+0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207).
I
H
45
PD78P322
(2) EV-9200G-80
Figure A-3. Drawing of Conversion Socket (EV-9200G-80) (For reference only)
F A B G N
S
T D C E U
R
EV-9200G-80-G0 INCHES 0.984 0.799 0.157 0.569 0.748 4-C 0.11 0.031 0.433 0.866 0.972 0.197 0.638 0.744 0.315 0.307 0.098 0.079 0.053 0.014+0.004 -0.005
0.091 0.059
O
P
EV-9200G-80
1 No.1 pin index Q
H I J ITEM A B C D E F G H I J K L M O N P Q R S T U MILLIMETERS 25.0 20.30 4.0 14.45 19.0 4-C 2.8 0.8 11.0 22.0 24.7 5.0 16.2 18.9 8.0 7.8 2.5 2.0 1.35 0.35 0.1
2.3 1.5
46
M
K
L
PD78P322
Figure A-4. Recommended Footprint of Conversion Socket (EV-9200G-80) (For reference only)
G H
L
D
E
F
J
M C B A EV-9200G-80-P0 INCHES 1.012 0.827 0.031+0.002 -0.001 x 0.906=0.724 +0.003 -0.002 0.598 0.783 0.433+0.004 -0.003 0.217+0.001 -0.002 0.197+0.003 -0.004 0.098+0.002 -0.001 0.02+0.001 -0.002
ITEM A B C D E F G H I J K L M Caution
MILLIMETERS 25.7 21.0 0.80.02 x 23=18.40.05
0.80.02 x 15=12.00.05 0.031+0.002 x 0.591=0.472 +0.003 -0.001 -0.002 15.2 19.9 11.00 0.08 5.50 0.03 5.00 0.08 2.50 0.03 0.5 0.02
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.062+0.001 -0.002
Dimensions of mount pad for EV-9200 and that for target device (QFP) may be different in some parts. For the recommended mount pad dimensions for QFP, refer to "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (IEI-1207).
K
I
47
PD78P322
*
APPENDIX B. TOOLS
B.1 Development Tools The following development tools are readily available to support development of systems using the PD78P322: Language Processor
78K/III Series relocatable assembler (RA78K/III) Relocatable assembler common to the 78K/III series. Since it contains the macro function, the development efficiency can be improved. A structured assembler which enables you to explicity describe program control structure is also attached and program productivity and maintenance can be improved. Host machine OS PC-9800 series MS-DOS
TM
Ordering code Supply medium 3.5-inch 2HD 5-inch 2HD (product name)
S5A13RA78K3 S5A10RA78K3 S7B13RA78K3 S7B10RA78K3 S3P16RA78K3 S3K15RA78K3 S3R15RA78K3
IBM PC/AT
TM
PC DOS
TM
3.5-inch 2HC 5-inch 2HC
and compatible machine HP9000 series 700TM SPARCstationTM NEWS 78K/III Series C compiler (CC78K/III)
TM
HP-UXTM SunOSTM NEWS-OS
TM
DAT Cartridge tape (QIC-24)
C compiler common to the 78K/III series. This is a program to convert a program written in C language into an object code executable with a microcontroller. When using the compiler, 78K/III series relocatable assembler (RA78K/III) is necessary. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT
TM
Ordering code (product name)
S5A13CC78K3 S5A10CC78K3 S7B13CC78K3 S7B10CC78K3 S3P16CC78K3 S3K15CC78K3 S3R15CC78K3
PC DOS
3.5-inch 2HC 5-inch 2HC
and compatible machine HP9000 series 700 SPARCstation NEWS HP-UX SunOS NEWS-OS
DAT Cartridge tape (QIC-24)
Remark The operation of the relocatable assembler and C compiler is guaranteed only on the host machine under the operating systems listed above.
48
PD78P322
PROM Write Tools
Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single chip microcontrollers containing PROM by stand-alone or host machine operation by connecting an attached board and optional programmer adapter to PG-1500. It also enables you to program typical PROM devices of 256K bits to 4M bits. UNISITE 2900 PA-78P322GF PA-78P322GJ PA-78P322K PA-78P322KC PA-78P322KD PA-78P322L PROM programmer adapters to write programs onto the PD78P322 on a general purpose PROM programmer such as PG-1500. PA-78P322GF ... PD78P322GF PA-78P322GJ ... PD78P322GJ PA-78P322K ... PD78P322K PA-78P322KC ... PD78P322KC PA-78P322KD ... PD78P322KD PA-78P322L ... PD78P322L Software PG-1500 controller Connects PG-1500 and a host machine by a serial or parallel interface and controlls PG-1500 on the host machine. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HD 5-inch 2HC Ordering code (product name) PROM programmer manufactured by Data I. O. Japan.
S5A13PG1500 S5A10PG1500 S7B13PG1500 S7B10PG1500
Remark The operation of the PG-1500 controller is guaranteed only on the host machine under the operating systems listed above.
49
PD78P322
Debugging Tools
Hardware IE-78327-R IE-78320-R
Note
IE-78327-R and IE-78320-R are in-circuit emulators that can be used for application system development and debugging. Connect a host machine for debugging. IE-78327-R can be used in common for the PD78322 subseries and the PD78328 subseries. IE-78320-R can be used for the PD78322 subseries.
EP-78320GF-R EP-78320GJ-R EP-78320L-R
Emulation probe to connect IE-78327-R or IE-78320-R to the target system. EP-78320GF-R ................. 80-pin plastic QFP EP-78320GJ-R .................. 74-pin plastic QFP EP-78320L-R .................... 68-pin plastic QFJ
Software
IE-78327-R control program (IE controller)
Program to control IE-78327-R on a host machine. Automatic execution of commands, etc., is enabled for more efficient debugging. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HC 5-inch 2HC Ordering code (product name)
S5A13IE78327 S5A10IE78327 S7B13IE78327 S7B10IE78327
IE-78320-R control program Note (IE controller)
Program to control IE-78320-R on a host machine. Automatic execution of commands, etc., is enabled for more efficient debugging. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 5-inch 2HC Ordering code (product name)
S5A13IE78320 S5A10IE78320 S7B10IE78320
Remarks
1. 2.
The operation of the IE controller is guaranteed only on the host machine under the operating systems listed above.
PD78322 subseries:
PD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1),
78320(A2), 78322(A), 78322(A1), 78322(A2), 78323(A), 78323(A1), 78323(A2), 78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1), 78P324(A2)
PD78328 subseries:
PD78327, 78328, 78P328, 78327(A), 78328(A)
Note Conventional IE-78320-R is a maintenance product. When purchasing a new incircuit emulator, use an alternative product IE-78327-R.
50
Development Tool Configuration
Host machine PC-9800 series or IBM PC/AT
RS-232-C
Emulation probe
Software
IE-78327-R In-circuit emulator
RS-232C PROM programmer EP-78320GF-R EP-78320L-R EP-78320GJ-R + + Socket to connect emulation probe and target systemNote EV-9200G-80 EV-9200G-74
Relocatable assembler PG-1500 IE controller controller (with structured assembler)
On-chip PROM version
PG-1500
Socket for plastic QFJ
PD78P322GF PD78P322GJ PD78P322L
PD78P322K PD78P322KC PD78P322KD
+ + Programmer adapter
+
Target system
PA-78P322GF PA-78P322GJ
PA-78P322L
PD78P322K PD78P322KC PD78P322KD
PD78P322
Note
The socket is attached to the emulation probe.
Remarks The host machine and PG-1500 can be connected directly by RS-232-C.
51
PD78P322
B.2 Evaluation Tools The following evaluation tools are provided to evaluate the PD78P322 function:
Ordering Code (product name) EB-78320-98 PC-9800 series The PD78P322 function can be easily evaluated by connecting the evaluation tool to a host machine. The EB-78320-98/PC command system basically is compliant with the EB-78320-PC IBM PC/AT and compatible machine IE-78327-R or IE-78320-R command system. Thus, easy transition to application system development process by IE-78327-R or IE-78320-R can be made. The evaluation tools enable turbo access manager (PD71P301)Note to be mounted on the printed circuit board. Host Machine Function
Note Turbo access manager (PD71P301) is available for maintenance purpose only. Cautions 1. 2. EB-78320-98/PC is not the PD78P322 application system development tool. EB-78320-98/PC does not contain the emulation function at internal PROM execution of the
PD78P322.
B.3 Embedded Software The following embedded software products are readily available to support more efficient program development and maintenance: Real-time OS
Real-time OS (RX78K/III) The purpose of RX78K/III is to realize a multi-task environment in a control area which requires real-time processing. RX78K/III allocates idle times of CPU to other processing to improve overall performance of the system. RX78K/III provides a system call based on the ITRON specification. RX78K/III assembler package provides the RX78K/III nucleus and a tool (configurator) to prepare multiple information tables. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HC 5-inch 2HC Ordering code (product name)
S5A13RX78320 S5A10RX78320 S7B13RX78320 S7B10RX78320
Caution When purchasing the RX78K/III, fill in the purchase application form in advance, and sign the User's Agreement. Remark When using the RX78K/III Real-time OS, the RA78K/III assembler package (option) is necessary.
52
PD78P322
Fuzzy Inference Development Support System
Fuzzy Knowledge Data Preparation Tool (FE9000, FE9200) Program supporting input of fuzzy knowledge data (fuzzy rule and membership function), input/editing (edit), and evaluation (simulation). Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine Translator (FT78K3)
Note
Ordering code (product name)
S5A13FE9000 S5A10FE9000 S7B13FE9200 S7B10FE9200
PC DOS WindowsTM 3.5-inch 2HC 5-inch 2HC
Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation tool to the assembler source program for the RA78K/III. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HC 5-inch 2HC Ordering code (product name)
S5A13FT78K3 S5A10FT78K3 S7B13FT78K3 S7B10FT78K3
Fuzzy Inference Module (FI78K/III)Note
Program executing fuzzy inference. Fuzzy inference is executed by linking fuzzy knowledge data converted by translator. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HC 5-inch 2HC Ordering code (product name)
S5A13FI78K3 S5A10FI78K3 S7B13FI78K3 S7B10FI78K3
Fuzzy Inference Debugger (FD78K/III)
Support software evaluating and adjusting fuzzy knowledge data at hardware level by using in-circuit emulator. Host machine OS PC-9800 series MS-DOS Supply medium 3.5-inch 2HD 5-inch 2HD IBM PC/AT and compatible machine PC DOS 3.5-inch 2HC 5-inch 2HC Ordering code (product name)
S5A13FD78K3 S5A10FD78K3 S7B13FD78K3 S7B10FD78K3
Note Under development
53
PD78P322
[MEMO]
54
PD78P322
NOTES FOR CMOS DEVICES (1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
(2) HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
(3) STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
QTOP is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON.
55
PD78P322
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: PD78P322K, 78P322KC, 78P322KD The customer must judge the need for license: PD78P322GF-3B9, 78P322GJ-5BJ, 78P322L
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11

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